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Publications

  • Improving the Error Behavior of DRAM by Exploiting its Z-Channel Property
    K. Kraft, M. Jung, C. Sudarshan, D. M. Mathew, C. Weis, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE) March, 2018, Dresden, Germany
  • An Analysis on Retention Error Behavior and Power Consumption of Recent DDR4 DRAMs
    D, M. Mathew, M. Schultheis, C. C. Rheinländer, C. Sudarshan, M. Jung, C. Weis, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE) , March, 2018, Dresden, Germany
  • A Memory Centric Architecture of the Link Assessment Algorithm in Large Graphs
    C. Brugger, V. Grigorovici, M. Jung, C. De Schryver, C. Weis, N. Wehn, K. Zweig. IEEE Design & Test , 2017
  • Integrating DRAM Power-Down Modes in gem5 and Quantifying their Impact
    R. Jagtap, M. Jung, W. Elsasser, C. Weis, A. Hansson, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2017) , October, 2017, Washington, DC, USA
  • Using Run-Time Reverse-Engineering to Optimize DRAM Refresh
    D. M. Mathew, É. F. Zulian, M. Jung, K. Kraft, C. Weis, B. Jacob, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2017), October, 2017, Washington, DC, USA
  • A New State Model for DRAMs Using Petri Nets
    M. Jung, K. Kraft, N. Wehn. IEEE In­ter­na­tio­nal Con­fe­rence on Em­bed­ded Com­pu­ter Sys­tems Ar­chi­tec­tu­res Mo­de­ling and Si­mu­la­ti­on (SAMOS), July, 2017, Samos Is­land, Greece.
  • A Platform to Analyze DDR3 DRAM’s Power and Retention Time
    M. Jung, D. Mathew, C. Rheinländer, C. Weis, N. Wehn. IEEE Design & Test, 2017.
    Link
  • A Bank-Wise DRAM Power Model for System Simulations
    D. M. Mathew, É. F. Zulian, S. Kannoth, M. Jung, C. Weis, N. Wehn. International Conference on High-Performance and Embedded Architectures and Compilers 2017 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2017, Stockholm, Sweden.
  • DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool (DOI)
    C. Weis, A. Mutaal, O. Naji, M. Jung, A. Hansson, N. Wehn. International Journal of Parallel Programming (IJPP), Springer, 2016.
  • ConGen: An Application Specific DRAM Memory Controller Generator
    M. Jung, I. Heinrich, M. Natale, D. Mathew, C. Weis, S. Krumke, N. Wehn. International Symposium on Memory Systems (MEMSYS 2016), October, 2016, Washington, DC, USA.
  • Reverse Engineering of DRAMs: Row Hammer with Crosshair
    M. Jung, C. Rheinländer, C. Weis, N. Wehn. International Symposium on Memory Systems (MEMSYS 2016), October, 2016, Washington, DC, USA.
  • 3D Memories
    C. Weis, M. Jung, N. Wehn. Accepted for publication, Book chapter in the Handbook of 3D Integration Vol 4, Wiley-VCH, 2016.
  • A New Bank Sensitive DRAMPower Model for Efficient Design Space Exploration
    M. Jung, D. Mathew, É. Zulian, C. Weis, N. Wehn. International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2016), September, 2016, Bremen, Germany.
  • Exploring System Performance using Elastic Traces: Fast, Accurate and Portable
    R. Jagtap, S. Diestelhorst, A. Hansson, M. Jung, N. Wehn, IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2016, Samos Island, Greece.
  • Approximate Computing with Partially Unreliable Dynamic Random Access Memory: Approximate DRAM
    M. Jung, D. Mathew, C. Weis, N. Wehn. In Proc. IEEE/ACM Design Automation Conference (DAC), June, 2016, Austin, TX, USA.
  • Efficient Reliability Management in SoCs - An Approximate DRAM Perspective
    M. Jung, D. Mathew, C. Weis, N. Wehn. 21st Asia and South Pacific Design Automation Conference (ASP-DAC), Special Session: Cross-Layer Resilience: Snapshots from the Frontier of Design, January, 2016, Macao, China.
  • A Cross Layer Approach for Efficient Thermal Management in 3D Stacked SoCs
    M. Jung, C. Weis, N. Wehn. Journal of Microelectronics Reliability, Elsevier 2015.
  • Reliability and Thermal Challenges in 3D Integrated Embedded Systems
    C. Weis, M. Jung, N. Wehn. 1st International ESWEEK Workshop on Resiliency in Embedded Electronic Systems, October, 2015, Amsterdam, The Netherlands.
  • Omitting Refresh - A Case Study for Commodity and Wide I/O DRAMs
    M. Jung, Éder Zulian, M. Mathew, M. Herrmann, C. Brugger, C. Weis, N. Wehn. 1st International Symposium on Memory Systems (MEMSYS 2015), October, 2015, Washington, DC, USA.
  • DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework
    M. Jung, C. Weis, N. Wehn. IPSJ Transactions on System LSI Design Methodology (T-SLDM), August, 2015.
    Link
  • A High-Level DRAM Timing, Power and Area Exploration Tool
    O. Naji, A. Hansson, C. Weis, M. Jung, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2015, Samos Island, Greece.
    Link
  • Thermal Aspects and High-level Explorations of 3D stacked DRAMs
    C. Weis, M. Jung, C. Santos, P. Vivet, O. Naji, A. Hansson, N. Wehn. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July, 2015, Montpellier, France.
  • Retention Time Measurements and Modelling of Bit Error Rates of WIDE-I/O DRAM in MPSoCs C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2015, Grenoble, France.
  • Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs
    M. Jung, M. Sadri, C. Weis, N. Wehn, L. Benini., VLSI-SoC, October, 2014, Playa del Carmen, Mexico.
  • Thermal Modelling of 3D Stacked DRAM with Virtual Platforms
    M. Jung, M. Sadri, C. Weis, N. Wehn. HiPEAC info 38 (Page 10), www.hipeac.net, May, 2014.
  • Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization
    K. Chandrasekar, S. Goossens, C. Weis, M. Koedam, B. Akesson, N. Wehn, K. Goossens. Conference Design, Automation and Test in Europe (DATE), April, 2014, Dresden, Germany.
  • Energy Optimization in 3D MPSoCs with Wide-I/O DRAM
    M. Sadri, M. Jung, C. Weis, N. Wehn, L. Benini. Conference Design, Automation and Test in Europe (DATE), March, 2014, Dresden, Germany.
  • Hybrid Memory Architecture for Voltage Scaling in Ultra-Low-Power Multi-Core Biomedical Processors
    D. Bortolotti, A. Bartolini, C. Weis, D. Rossi, L. Benini. Conference Design, Automation and Test in Europe (DATE), March, 2014, Dresden, Germany.
  • Virtual Platforms for Fast Memory Subsystem Exploration Using gem5 and TLM2.0
    M. Jung, M. Sadri, N. Wehn. Ninth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES13), July, 2013, Fiuggi, Italy.
    PDF
  • TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems
    M. Jung, Work-in-Progress Poster Session. IEEE/ACM Design Automation Conference (DAC), June, 2013, Austin, TX, USA.
  • Power Modelling of 3D-Stacked Memories with TLM2.0 based Virtual Platforms
    M. Jung, C. Weis, P. Bertram, G. Braun, N. Wehn. Synopsys User Group Conference (SNUG), May, 2013, Munich, Germany.
    Link
  • Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach
    K. Chandrasekar, C. Weis, B. Akesson, N. Wehn, K. Goossens. IEEE/ACM Design Automation Conference (DAC), June, 2013.
  • Virtual Platforms for Memory Controller Design Space Exploration
    M. Jung, Designers Track Talk. IEEE/ACM Design Automation Conference (DAC), June, 2013, Austin, TX, USA.
  • Exploration and Optimization of 3-D Integrated DRAM Subsystems
    C. Weis, I. Loi, L. Benini, N. Wehn. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 32, Issue 4, Pages 597-610, April, 2013, New York, US. Link
  • System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs
    K. Chandrasekar, C. Weis, B. Akesson, N. Wehn, K. Goossens. In Proc. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2013, Grenoble, France.
  • TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration
    M. Jung, C. Weis, N. Wehn, K. Chandrasekar. International Conference on High-Performance and Embedded Architectures and Compilers 2013 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2013, Berlin.
    Link
  • Modelling 3D-Stacked Memories with Virtual Platforms
    M. Jung, C. Weis, N. Wehn. HiPEAC info 32 (Pages 12-13), www.hipeac.net, October, 2012.
    Link
  • An Energy Efficient DRAM Subsystem for 3D integrated SoCs
    C. Weis, N. Wehn, I. Loi, L. Benini. In Proc. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2012, Dresden, Germany.
    Link
  • DRAM Selection and Configuration for Real-Time Mobile Systems
    M. D. Gomony, C. Weis, B. Akesson, N. Wehn and K. Goossens. In Proc. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2012, Dresden, Germany.
    Link
  • Design Space Exploration for 3D-stacked DRAMs
    C. Weis, N. Wehn, I. Loi, L. Benini. In Proc. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2011, Grenoble, France.
    Link