Microelectronic Systems Design Research Group

DRAMSys

Approximately-Timed TLM Models for DDR and Wide I/0 DRAM
TU Kaiserslautern

To tackle the challenges of todays memory systems with respect to applications, performance, power, temperature, retention errors and di erent DRAM architectures a holistic exploration framework is needed. [2]
DRAMSys supports following flow:

  • DRAMSys consists of models that are reflecting the DRAM functionality, power (DRAMPower), temperature (IceWrapper) and retention time errors [3].
  • With these models system designers are able to analyse the limiting parameters and issues. Therefore, the framework provides several analysis tools that assist the designer.
  • With this valuable insights the designer is able to optimise the DRAM subsystem with respect to the controller architecture, power and thermal management as well as device selection and channel configuration for a specific application.


This detailed DRAM model of DRAMSys is based on Approximately-Timed TLM. Towards this, we introduced a new DRAM specific TLM protocol [1] to obtain the needed accuracy to analyse the impact of different scheduling algorithms or arbitration schemes on the latency and power on system level, while improving simulation speed. For analysing, verifying and evaluation of the memory access DRAMSys provides a user friendly Trace Analyser tool.

 

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DRAMSys Analyzer

Thermal Simulation of MPSoCs with Wide-I/O DRAM

References

[1] TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration 
M. Jung, C. Weis, N. Wehn, K. Chandrasekar. International Conference on High-Performance and Embedded Architectures and Compilers 2013 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2013, Berlin. 
[2] DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework
M. Jung, C. Weis, N. Wehn. IPSJ Transactions on System LSI Design Methodology (T-SLDM), October, 2015.
[3] Retention Time Measurements and Modelling of Bit Error Rates of WIDE-I/O DRAM in MPSoCs
C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2015, Grenoble, France.
[4] Energy Optimization in 3D MPSoCs with Wide-I/O DRAM
M. Sadri, M. Jung, C. Weis, N. Wehn, L. Benini. Conference Design, Automation and Test in Europe (DATE), March, 2014, Dresden, Germany.
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